Dual uplink code for LCU FPGA 

The files for the LCU FPGA for the 7123 (including TOYO) systems dual uplink with dual MPA and non dual MPA versions are included.

lcuBA2C.bin  dual uplink, dual MPA
lcuB22C.bin  dual uplink, non dual MPA

In the dual MPA version addresses 2A and 2B are directed to the LCU card transmitter port (TX1 port - J2), 2C to the first mezzanine transmitter port (TX2 port - J7) and 2D to the second mezzanine transmitter port (TX3 port - J8). Note that the ALL command is sent to all ports including the third mezzanine transmitter port (TX4 port - J4).

The non dual MPA version obeys the current standard: address 2A to the LCU card transmitter port (TX1 port - J2), 2B to the first mezzanine transmitter port (TX2 port - J7), 2C to the second mezzanine transmitter port (TX3 port - J8), 2D to the third mezzanine transmitter port (TX4 port - J4) and the ALL command being sent to all the ports

These have the 80 Mb downlink connection to the IOP Wet.

Power sequencing is under control of the DSP, with all the relevant switches being in the off state upon download.

Both versions have BITE enabled.

Please see the enclosed document lcucfg.doc for the meaning of the relevant bits in the LCU FPGA configuration register.

Rev B FPGA code for LCU

This revision improves the transmit phy interface timing but is functionally the same as the corresponding versions for rev A

lcuBA2C.bin/lcuBA2C.bit  dual mpa, dual uplink
lcuB22C.bin/lcuB22C.bit  non dual mpa, dual uplink

